First, the data input stage
1. Is the information received in the process complete (including: schematic, *.brd file, bill of materials, PCB design description and PCB design or change requirements, standardization requirements description, process design documentation)
2. Confirm that the PCB template is up to date
3. Confirm that the positioning device of the template is in the correct position.
4. PCB design description and PCB design or change requirements, standardization requirements are clear
5. Confirm that the non-provisioning device and wiring area on the outline drawing have been reflected on the PCB template.
6. Compare the outline drawing to confirm that the dimensions and tolerances marked on the PCB are correct. The metallized holes and non-metallized holes are defined accurately.
7. After confirming that the PCB template is accurate, it is best to lock the structure file to avoid misoperation.
Second, the post-layout inspection stage
a. device inspection
8. Confirm that all device packages are consistent with the company’s unified library. Have you updated the package library (check the run results with viewlog). If they are inconsistent, be sure to update Symbols.
9, the mother board and the daughter board, the single board and the back board, the confirmation signal corresponds, the position corresponds, the connector direction and the silk screen mark are correct, and the daughter board has anti-missing measures, and the device on the daughter board and the motherboard should not interfere.
10, whether the component is 100% placed
11. Open the place-bound of the device TOP and BOTTOM layers to see if the DRC caused by the overlap is allowed.
12, Is Mark enough and necessary?
13, heavier components should be placed close to the PCB support or support side to reduce PCB warpage
14, the structure-related components are best locked after the board is installed, to prevent misoperation of the moving position
15, within 5mm around the crimping socket, components with a height exceeding the height of the crimping socket are not allowed on the front side, and components or solder joints are not allowed on the back side.
16, confirm whether the device layout meets the technical requirements (focus on BGA, PLCC, patch socket)
17, metal shell components, pay special attention not to touch other components, leaving enough space
18. Interface-related devices are placed as close as possible to the interface. The backplane bus driver is placed as close as possible to the backplane connector.
19. Whether the CHIP device of the wave soldering surface has been converted into a wave soldering package.
20, whether there are more than 50 manual solder joints
21, horizontally insert higher components on the PCB, should consider horizontal installation. Leave room for lying. And consider fixed ways, such as the fixed pad of the crystal
22, need to use the heat sink device, confirm that there is enough space with other devices, and pay attention to the height of the main device within the heat sink range
b. Function check
23, Whether the digital circuit of the digital-analog hybrid board and the analog circuit device layout have been separated, and the signal flow is reasonable.
24, A / D converter placed across the modulus partition.
25, Is the clock device layout reasonable?
26, Is the layout of high-speed signal devices reasonable?
27, Whether the termination device is properly placed (the source matching string resistance should be placed at the driving end of the signal; the intermediate matching string resistance is placed at the middle position; the terminal matching string resistance should be placed at the receiving end of the signal)
28, Is the number and location of decoupling capacitors of IC devices reasonable?
29, the signal line uses a plane of different levels as a reference plane, and when the area is divided across the plane, whether the connection capacitance between the reference planes is close to the trace area of the signal.
30, Is the layout of the protection circuit reasonable and advantageous for segmentation?
31, Is the fuse of the single board power supply placed near the connector and there are no circuit components in front?
32, confirm that the strong signal and weak signal (power difference of 30dB) circuit is laid separately
33. Whether to place devices that may affect EMC experiments in accordance with design guidelines or reference to successful experience. For example, the reset circuit of the panel should be slightly closer to the reset button.
34, heat sensitive components (including liquid dielectric capacitors, crystal oscillators) as far away as possible from high-power components, heat sinks and other heat sources
35, Whether the layout meets the thermal design requirements, the heat dissipation channel (performed according to the process design file)
d. Power supply
36, Is the IC power supply too far from the IC?
37, LDO and surrounding circuit layout is reasonable
38, Is the circuit layout of the module power supply reasonable?
39, is the overall layout of the power supply reasonable?
e. Rule settings
40, Whether all simulation constraints have been correctly added to the Constraint Manager
41, Is the physical and electrical rules set correctly (note the constraint settings of the power network and the ground network)
42, Test Via, Test Pin spacing is enough
43, Whether the thickness and solution of the laminate meet the design and processing requirements
44, Whether all differential line impedances with characteristic impedance requirements have been calculated and controlled by rules
Third, the post-wiring inspection stage
a. Digital model
45. Is the trace of the digital circuit and the analog circuit separated, and the signal flow is reasonable?
46, A / D, D / A and similar circuits If the ground is split, then the signal line between the circuits is from the bridge point between the two places (except for differential lines)?
47. The signal line that must cross the gap between the split power supplies should refer to the complete ground plane.
48. If the stratum design partition is not split, ensure that the digital signal and analog signal are partitioned.
b. Clock and high speed parts
49, Is the impedance of each layer of the high-speed signal line consistent?
50, High-speed differential signal lines and similar signal lines, are they equal, symmetrical, and nearly parallel?
51, confirm the clock line as far as possible in the inner layer
52, confirm whether the clock line, high-speed line, reset line and other strong radiation or sensitive lines have been wired as much as possible according to the 3W principle.
53, Is there a test point for the fork, clock, interrupt, reset signal, 100 Mbps/Gigabit Ethernet, high speed signal?
54, Is LVDS and other low-level signals and TTL/CMOS signals as close as possible to 10H (H is the height of the signal line from the reference plane)?
55. Do clock lines and high-speed signal lines avoid crossing dense via via areas or routing between device pins?
56, Whether the clock line has met (SI constraint) requirements (whether the clock signal trace is less punched, the trace is short, the reference plane is continuous, the main reference plane is GND as much as possible; if the layer is changed, the GND main reference plane is changed. The layer is a GND via within 200 mils of the via.) If the main reference plane of different levels is changed when changing layers, is there a decoupling capacitor within 200 mils of the via?
57, differential pairs, high-speed signal lines, all types of BUS have met (SI constraints) requirements
c.EMC and reliability
58, For the crystal, is it layered underneath? Did you avoid signal lines crossing between device pins? For high-speed sensitive devices, is the signal line avoided from crossing between the device pins?
59. There should be no acute angle and right angle on the signal line of the board (usually a continuous turn at a 135 degree angle, and the RF signal line is preferably a circular arc or a calculated angled copper foil)
60. For the double panel, check whether the high-speed signal line is wired close to the ground return line. For the multi-layer board, check whether the high-speed signal line is as close as possible to the ground plane.
61. For adjacent two-layer signal traces, try to trace them vertically.
62, Avoid signal lines crossing from power modules, common mode inductors, transformers, filters
63, try to avoid long-distance parallel lines of high-speed signals on the same layer
64. Is there a shielded via on the edge of the board with digital ground, analog ground, and protective ground? Are multiple ground planes connected by vias? Is the via distance less than 1/20 of the wavelength of the highest frequency signal?
65. Is the signal trace corresponding to the surge suppression device short and thick at the surface?
66, confirm that the power supply, the formation has no islands, no excessive slotting, no long ground plane cracks due to over-sized or large-diameter through-hole isolation discs, no slender strips and narrow channels
67, Is there a hole in the ground where the signal line is more than one layer (at least two ground planes are required)?
h. Power and ground
68. If the power/ground plane is split, try to avoid high-speed signal crossing on the split reference plane.
69. Confirm that the power supply and ground can carry enough current. Whether the number of vias meets the requirements of the load, (estimation method: 1A/mm line width when the outer copper thickness is 1oz, 0.5A/mm line width of the inner layer, double current of the short line)
70, Does the voltage drop requirement be met for power supplies with special requirements?
71, in order to reduce the edge radiation effect of the plane, the 20H principle should be met as much as possible between the power supply layer and the ground layer. (If conditions permit, the more the power layer is indented, the better).
72. If there is a division of the ground, does the divided land not constitute a loop?
73. Do different power planes in adjacent layers avoid overlapping placement?
74. Is the isolation of the protective ground, -48V ground and GND greater than 2mm?
75, -48V is just a signal return of -48V, not connected to other places? If you can’t do it, please explain the reason in the remarks column.
76. Is there a protective ground of 10~20mm near the connector panel and connect the layers with two rows of staggered holes?
77. Is the distance between the power cable and other signal lines meeting the safety requirements?
d. Prohibited area
78, under the metal shell device and the heat sink, there should be no traces, copper bumps and vias that may cause short circuits.
79, There should be no traces, copper bumps and vias around the mounting screws or washers that may cause short circuits.
80, whether there is a reserved position in the design requirements
81, the distance between the delamination line and the copper foil in the non-metallized hole should be greater than 0.5mm (20mil), and the outer layer should be 0.3mm (12mil). The spacing between the delamination line and the copper foil in the shaft hole of the single-layer drawing wrench should be greater than 2mm (80mil). )
82, copper and wire to the edge of the board is recommended to be greater than 2mm and minimum is 0.5mm
83, inner layer of copper to the edge of the board 1 ~ 2 mm, the minimum is 0.5mm
j. pad outlet
84. For two pad-mounted CHIP components (0805 and below), such as resistors and capacitors, the traces connected to their pads are preferably drawn symmetrically from the center of the pad and printed on the pad. Lines must have the same width. For lead lines with a line width of less than 0.3 mm (12 mil), this rule may not be considered.
85. Is the pad connected to the wider trace preferably transitioned through a narrow trace? (0805 and below package)
86, the line should be pulled out from the two ends of the pads of SOIC, PLCC, QFP, SOT, etc.
e. silk screen
87, Is the device bit number missing, and the position can correctly identify the device?
88, device bit number meets company standard requirements
89, confirm the pin arrangement order of the device, the first pin mark, the polarity mark of the device, and the correctness of the direction mark of the connector.
90, whether the board direction indicator of the motherboard and the daughter board corresponds to
91. Does the backplane correctly identify the slot name, slot number, port name, and jacket direction?
92, confirm that the silkscreen added by the design is correct.
93, confirm that the anti-static and RF board identification has been placed (use of RF board)
f. Encoding / barcode
94, confirm that the PCB code is correct and in line with company specifications
95, Confirm that the PCB coding position and level of the board are correct (should be on the upper left side of the A side, the silk screen layer)
96, confirm that the PCB coding position and level of the backplane are correct (should be on the upper right side of B, the outer copper foil surface)
97, confirm that there is barcode laser printing white silk screen marking area
98, confirm that there is no connection below the barcode box and a via hole larger than 0.5mm
99, confirm that the bar code can not have more than 25mm in height within 20mm outside the white silk screen area.
100, On the reflowed surface, vias cannot be designed on the pads. (The spacing between the normal window opening and the pad should be greater than 0.5mm (20mil). The distance between the green oil covered via and the pad should be greater than 0.1mm (4mil). Method: Open Same Net DRC, check DRC, Then close Same Net DRC)
101, the arrangement of the vias should not be too dense to avoid causing large breaks in the power supply and ground plane.
102, the hole diameter of the hole is preferably not less than 1/10 of the thickness of the plate.
103, Is the device placement rate 100%, and whether the routing rate is 100% (the need to do 100% is explained in the remarks)
104, whether the Dangling line has been adjusted to the minimum, and the confirmed Dangling line has been confirmed one by one;
105, Has the process problem of the process department feedback been carefully checked?
k. Large area copper foil
106, For large-area copper foil on Top and bottom, if there is no special need, apply grid copper [slanting net for single board, orthogonal net for back board, line width 0.3mm (12 mil), spacing 0.5mm ( 20mil)]
107, the component pads of the large-area copper foil area should be designed as flower pads to avoid solder joints; when there is current demand, first consider widening the ribs of the flower pads, then consider the full connection.
108. When copper is covered in large areas, you should try to avoid dead copper (island) without network connection.
109, large area copper foil should also pay attention to whether there is illegal connection, unreported DRC
l. test point
110, Is there enough test points for various power sources and grounds (at least one test point per 2A current)
111, confirm that the network without test points is confirmed to be streamlined
112, confirm that there is no test point set on the plug-in that is not installed at the time of production.
113, Test Via, Test Pin is already Fixed (suitable for testing the needle bed unchanged)
114, Test via and Test pin’s Spacing Rule should be set to the recommended distance first, check the DRC, if there is still DRC, then check the DRC with the minimum distance setting.
115, open the constraint set to open, update the DRC, check whether there is an impermissible error in the DRC
116, confirm that the DRC has been adjusted to the minimum, and confirm that the DRC cannot be eliminated;
n. optical positioning point
117, confirm that the PCB surface of the mounted component has an optical positioning symbol
118, confirm that the optical positioning symbol is not pressed (screen printing and copper foil routing)
119, the background of the optical positioning point needs to be the same, confirm that the entire board uses the optical point whose center is ≥5mm from the edge
120. Confirm that the optical positioning reference symbol of the entire board has been assigned coordinate values (the optical positioning reference symbol is recommended to be placed in the form of the device) and is an integer value in millimeters.
121, ICs with pin center distance <0.5mm, and BGA devices with center distance less than 0.8 mm (31 mil), optical positioning points should be placed near the diagonal of the component
o. Solder mask inspection
122, confirm whether there are special types of pads that are properly windowed (especially pay attention to hardware design requirements)
123, Is the via hole under the BGA processed into a cap plug hole?
124, In addition to testing the via hole, the via hole has been opened to open the small window or cover oil plug hole
125, Does the opening of the optical positioning point avoid the exposed copper and the exposed wire?
126, Power chip, crystal oscillator and other devices that need copper heat dissipation or ground shielding, whether there is copper skin and open the window correctly. Devices fixed by solder should have a large area of green oil to block solder diffusion
Fourth, the processing documents
a. drilling diagram
127, Notes PCB thickness, number of layers, silk screen color, warpage, and other technical explanations are correct
128, Whether the layer name, stacking order, medium thickness, and copper foil thickness of the stacked board are correct; whether impedance control is required, and the description is accurate. Whether the layer name of the stack chart is consistent with the name of the light drawing file
129, turn off the Repeat code in the setting table, and the drilling accuracy should be set to 2-5.
130, Whether the hole table and the drilling file are up to date (when changing the hole, it must be regenerated)
131, Is there an abnormal aperture in the hole table, the hole diameter of the crimping piece is correct; whether the hole diameter tolerance is correctly marked
132, Is the via of the plug hole listed separately and marked “filled vias”
133, the output of the light painting file should be in the RS274X format as much as possible, and the accuracy should be set to 5:5.
134, art_aper.txt is up to date (274X may not be needed)
135, whether there is an abnormal report in the log file of the output illuminating file
136, the edge of the negative layer and the island confirmation
137, Use the ray inspection tool to check whether the germination file matches the PCB (the comparison board should use the comparison tool for comparison)
Fifth, the file set
138, PCB file: Product model_Specification_Single board code_Version number.brd
139, backing plate design file: product model_specification_board code_version number-CB[-T/B].brd
140, PCB processing file: PCB code.zip (including all layers of illuminating files, aperture table, drilling files and ncdrill.log; jigsaw also need to provide the process of providing the puzzle file *.dxf), the backboard also Additional lining file: PCB code – CB[-T/B].zip (including drill.art, *.drl, ncdrill.log)
141, Process Design Document: Product Model_Specification_Single Board Code_Version Number-GY.doc
142, SMT coordinate file: product model_specification_board code_version number-SMT.txt, (When outputting the coordinate file, confirm the selection of the body center, only when confirming that the origin of all SMD device libraries is the device center Symbol origin)
143, PCB board structure file: product model_specification_board code_version number-MCAD.zip (including .DXF and .EMN files provided by structural engineers)
144, Test file: Product model_Specification_Single board code_Version number-TEST.ZIP (containment file containing testprep.log and untest.lst or *.drl test points)
145, Archive drawing file: product model specification – board name – version number. pdf, (including: cover, home page, each layer of silk screen, each layer of wiring, drilling diagram, back panel with lining diagram)
146, confirm the cover and home page information is correct
147, confirm the drawing serial number (corresponding to the order of the PCB layers) is correct
148, confirm that the PCB code on the drawing frame is correct.
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